Nonvolatile storage devices, such as NAND-based storage devices, include a translation layer that maps logical block addresses (LBAs) used by the host to access memory on the device into physical addresses in the nonvolatile memory. This translation layer is implemented in NAND-based storage devices as FTL tables. Because FTL tables must be accessed any time a host system desires to read a file from a storage device, latency in accessing FTL table entries can affect host device performance. In some high performance solid state drives (SSDs), the FTL table is stored in DRAM on the SSD to reduce latency. In such devices, the ratio of DRAM consumed for FTL tables to the total capacity of the device is 1 to 1,000, e.g., one megabyte of FTL table data is required to effectively address one gigabyte of NAND storage. The performance difference between accessing NAND storage and accessing device DRAM is considerable. For example, access to NAND for a read operation is typically a minimum of 50 to 70 microseconds per read while accessing device DRAM is on the order of hundreds of nanoseconds.
Because of the latency incurred by using device DRAM to cache FTL tables, one protocol, referred to as the nonvolatile memory express (NVMe) protocol includes a feature called the host memory buffer (HMB) which allows usage of host DRAM as a cache for FTL tables. HMB latency is on the order of ones of microseconds.
In some operating systems, such as in Windows environments, there is an architectural limit on the amount of host memory that can be allocated to direct access by peripheral component interface express (PCIe) devices. This memory must be dedicated from the non-paged pool and locked to specific physical addresses which the host cannot reallocate, limiting host memory efficiency. As a result, host environments are reluctant to allocate the full 1 to 1,000 ratio that would allow full mapping tables to be stored in the HMB.